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Figure 7.8 SDH frame structure

SDH is a TDM system where the total bandwidth of the ¬bre is considered to be one
channel. It is based on the same ISDN principles, and is made up of the basic telephone
network building block, the 64 kbps call. It is a synchronous system and therefore the
bits are transmitted at precise intervals, controlled by a master clock. An SDH frame is a
block of 2430 bytes of data, sent out every 125 µs, with empty frames being transmitted
if there is no data to send. The choice of 125 µs is because all digital telephone systems
use a sampling rate of 8000 frames/s. The basic transmission rate is therefore 8 — 2430 —
8000 = 155.52 Mbps (equivalent to 2430 64 kbps channels). This rate is referred to as
STM-1 (synchronous transmission module) and all other lines are multiples of this. Shown
in Figure 7.8 are two SDH STM-1 frames containing data.
The ¬rst nine columns of the frame are overhead. This comprises three rows of section
overhead, followed by six rows of line overhead. The ¬rst row of the line overhead con-
tains a pointer to the location of the ¬rst full cell. This byte is the ¬rst in a column of path
overhead, with the data area containing for example ATM cells. Note that as illustrated,
the data can be placed anywhere within the payload area and in fact, span more than one
area, allowing data such as ATM that is asynchronous to be transported ef¬ciently. For
example, if an ATM cell arrives even as an empty frame is being constructed, it is inserted
in the current frame rather than waiting for the next. To provide higher speeds of oper-
ation, the basic SDH building block, the STM-1, is multiplexed, to provide higher-order
STM signals, as shown in Figure 7.9.
Table 7.3 summarizes the SDH signals, the SONET equivalent, and the associated data
rates. Note that ATM was originally designed to travel over 155 Mbps. UMTS physical layer
In the context of UMTS, Table 7.4 presents the speci¬ed formats for the physical carriers
that may be used.
For reasons of reuse of existing infrastructure, the Iub interface will commonly be
implemented using PDH, perhaps in conjunction with inverse multiplexing for ATM, as

Multiplexer 1
STM-0 STM-4 fibre
-1 Multiplexer
M converter

Figure 7.9 SDH signals

Table 7.3 SDH multiplexed signals
SDH SONET Data rate
Electrical Optical

STM-0 STS-1 OC-1 51.84
STM-1 STS-3 OC-3 155.52
STM-4 STS-12 OC-12 622.08
STM-16 STS-48 OC-48 2488.32
STM-64 STS-192 OC-192 9953.28

Table 7.4 UMTS physical carriers
Carrier Data rate Carrier Data rate
scheme (Mbps) scheme (Mbps)
E1 2 STM-0 51
T1 1.5 STS-1 51
J1 1.5 STM-1 155
E2 8 STS-3c 155
J2 6.3 STM-4 622
E3 34 STS-12c 622
T3 45

described in Section 7.5.3. The Iu and Iur interfaces can utilize any of the above, but
generally will require at least 155 Mbps to support the volume of traf¬c resulting from
connection to multiple base stations.
When the cells are encapsulated in a protocol for transmission, the cells are placed
in the payload of that protocol. An example is shown in Figure 7.10, where ATM cells
are encapsulated in the structure of a 2 Mbps PDH line. The ATM cells are packed into
time slots 1“15 and 17“31. Time slot 0 is used for framing and time slot 16 is reserved
for signalling. Notice that there does not need to be an alignment between the ATM
cell boundaries and the PDH medium frame delineation other than aligning to an octet

Timeslot 1-15 Timeslot 17-31
ATM header

ATM header
ATM header

Frame alignment Reserved for signalling

Figure 7.10 Framing of ATM cells in 2 Mbps PDH frame

boundary. When there are no ATM cells to send, idle cells will be inserted to maintain
the cell rate. ATM cell delineation is performed by the header error control (HEC) as
described shortly.

In addition to the requirements of physical media for the major UMTS interfaces, ATM
equipment needs internal connections, where systems or equipment cards are directly
connected to each other. This type of situation arises where interface cards need to be
connected to an ATM switching fabric. For this, the ATM Forum has created the UTOPIA
standard. UTOPIA stands for Universal Test and Operations Physical Layer Interface for
ATM. It is a speci¬cation that covers the physical layer of operation and outlines an
open, common interface for the data and control connections between physical ATM
devices. Control primitives such as timing and synchronization are de¬ned within the
speci¬cations, and are controlled by a management entity. UTOPIA currently has four
levels de¬ned, providing for different data transfer rates and bus widths. The four levels
are shown in Table 7.5.
The ATM cells are clocked across the bus between devices. UTOPIA forms an interface
between the ATM layer and the physical layer, as illustrated in Figure 7.11.
As an example, in 8-bit mode, ATM cells are transferred across the interface as shown
in Figure 7.12.

7.5.2 Transmission convergence (TC) sublayer
The role of the TC layer can be summarized as shown in Table 7.6.

Table 7.5 UTOPIA levels
UTOPIA level Maximum data rate Maximum bus width
1 155 Mbps 8
2 622 Mbps 16
3 2.4 Gpbs 32
4 10 Gbps 32

ATM Layer

PHY Layer

control interface

Figure 7.11 UTOPIA model

ATM Layer ATM Layer

7 0 7 0
Payload 48 Header 1

byte transfer

ATM cell

byte transfer

Payload 1 Header 5
Header 5 Payload 1


Header 1 Payload 48

PHY Layer connection

Figure 7.12 UTOPIA cell transfer

Table 7.6 Key TC functions
Transmission Reception
Convert cells into bitstream Convert bitstream into cells
Pack cells into transmission frames Remove cells from transmission frames
Generate HEC Check HEC
Insert idle cells Remove idle cells Transmitting cells

It has been seen that each cell contains a 5-byte header. One byte of this is a checksum
which can detect errors and correct single-bit errors in the rest of the header. The checksum
is calculated using cyclic redundancy checking with the polynomial x 8 + x 2 + x + 1.
Often the header may contain mostly zeros, since low virtual path and channel numbers
are allocated ¬rst. Therefore, the CRC has a constant 01010101 added to it. Since the CRC
only checks for errors in the header and not the payload, it is referred to as the header

error control (HEC). There is no provision at this layer for protection of the payload data
since ATM assumes that the underlying medium provides reliability.
For an asynchronous medium or carrier, cells can be transmitted once they are ready.
However, ATM also needs to support interfacing with physical carriers that are syn-
chronous, such as the PDH schemes, resulting in a requirement for synchronous trans-
mission. Since the cells then have a timing requirement, what should ATM do if there
is no cell to send? In this case, the TC sublayer will generate idle cells to maintain the
timing scheme. The format of an idle cell is presented in Section 7.6. Receiving cells
For reasons of ef¬ciency, the ATM cell has no boundaries de¬ned and it is the job of
the TC sublayer to decide where one cell ends and the next begins from the incoming
bitstream. ATM is unusual in this respect as most protocols do de¬ne some mechanism
for establishing where frames begin and end. To add framing information, such as the
preamble used in Ethernet, would add a signi¬cant overhead to the cell, and detract from
the bene¬ts gained by using a small cell. It can be the case that the framing from the
underlying carrier may indicate the frame boundaries, but this is not guaranteed.
ATM overcomes this problem by using the HEC to provide the framing information.
Since, with carrier class equipment and reliable connections, the likelihood of a header
error is remote (as shown above), the HEC can take on this second role. The header is 5
bytes long so if the cell is valid, the ¬rst 40 bits can be examined, with the right 8 bits
used to check the remaining 32 bits, as shown in Figure 7.13.
If they match then the cell should be valid and the next 48 bytes will contain the
data. This is implemented using a 40-bit shift register. The bits are shifted in and the
HEC checked for validity. If it is not valid, all the bits are right-shifted and the next
bit brought in until it is valid. Is there a problem? What are the chances of a random
HEC being valid? The HEC only contains 8 bits, so therefore there is a probability
of 1/256! At the speed of operation of ATM, this probability is too high. However,
the probability of two random hits in succession is considerably lower, and for three,
lower still.
Therefore, a mechanism must be introduced to check for a number of correct HECs before
verifying that the incoming cells are synchronized and framed correctly. The scheme is
implemented by a ¬nite state machine. The details may be found in ITU-T I.432.1. Typically,
it checks for 4“6 correct headers in a row before assuming it has correct framing.


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